1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to an improved method for opening deep trenches through a relatively thick hard mask by employing a thinner resist layer.
2. Description of the Related Art
In the semiconductor industry, there is a great initiative to provide improved performance from smaller and smaller components. As with all semiconductor devices, semiconductor memories are pushed to the limits of performance. The capabilities of semiconductor memory components are often needed to perform at ever increasing levels from one generation of designs to the next. In one example, a need exists for increasing a capacitance value for deep trenches used for capacitor cells in dynamic random access memories.
Capacitance may be increased for deep trench capacitors by increasing the surface area of the storage node within the deep trench. However, increasing the length or width of the cell impacts the layout area of the semiconductor memory device since each row or column would have to increase by the augmented length and/or width of the new sized trenches. Therefore, this approach is not desirable.
The surface area of the storage node may also be increased by increasing the depth of the trench. This has proven to be a difficult task. The depth of the deep trenches has been limited by a hard mask used to etch the deep trench openings in a substrate.
Referring to FIG. 1, a semiconductor memory device 10 includes a substrate 12, preferably a silicon substrate. A pad stack 14 is deposited on the substrate 12. Pad stack 14 may include a silicon oxide layer 16 and a nitride layer 18. A hard mask layer 20 is formed on the pad stack 14. Hard mask layer 20 may include borosilicate glass, for example. An anti-reflection coating (ARC) 21 is deposited on hard mask layer 20 to assist in patterning a resist layer 22. Resist layer 22 is formed on ARC layer 21 and patterned over location where a deep trench will be etched in further processing steps. Resist layer 22 is relatively thick ranging from about 600 nm to about 800 nm in thickness. Resist layer 22 is required to be at least 600 nm in thickness to provide a sufficient amount of time to etch hard mask layer 20 and pad stack 14 in later steps.
Referring to FIG. 2, an etching process is performed to form a mask for etching substrate 12 to form deep trenches. The conventional process etches through ARC layer 21, hard mask layer 20 and pad stack 14. Although etching is selective to resist layer 22, resist layer 22 is eroded by the etching process and, therefore, a sufficient thickness must be maintained for resist layer 22. The etching continues until substrate 12 has been reached. Next, resist layer 22 and ARC layer 21 are removed from a top surface of the layer stack as shown in FIG. 3. This provides hard mask layer 20 on the top surface for etching substrate 12. It is to be understood that hard mask layer is between 600 nm and 700 nm in thickness. Larger thicknesses are avoided since etching larger thicknesses of hard mask layer 20 would require a thicker resist layer 22, and the thickness of resist layer 22 is limited by the lithographic process. If resist layer 22 becomes too thin during etching, scalloping occurs in the etched opening due to unavoidable damage on layer 22 by the etching process. This scalloping is undesirable and reduces the hard mask layer 20 thickness and thus reduces the possible depth of the trenches.
Referring to FIG. 4, hard mask layer 20 provides a selective etch mask for forming trenches 28 in substrate 12. Hard mask 20 is eroded during the etching process and therefore sufficient thickness of hard mask layer 20 must be provided. Unfortunately, the thickness of hard mask layer 20 is limited by the lithographic process and the thickness of resist layer 22, as described above. A hard mask layer that is thicker would require a thicker resist layer 22. Therefore, the thickness of hard mask layer is limited which results in a depth of trenches 28 which is also limited. Conventional trenches formed into substrate 12 are typically between about 6 microns and about 7 microns-deep for 0.2 micron groundrules. However, deeper trench depth is desirable to increase the capacitance value of trench capacitors to enhance device performance and yield.
Therefore, a need exists for a method for extending the depth of deep trenches in semiconductor devices. A further need exists for providing a method for permitting the use of thicker hard mask layers at a given resist thickness in processing of semiconductors.